IB Computer Science: Computer Architecture Types (SL & HL)

1) Von Neumann Architecture SL

Definition: Instructions and data share the same memory and same bus.

Key features

Single memory for both instructions and data
Sequential execution controlled by a program counter
Simple design

Exam tip (must mention)

Von Neumann bottleneck: the CPU cannot fetch an instruction and data at the same time, so throughput can be limited.

Simple diagram

CPU ── single bus ── Memory (instructions + data)

3) Processor Types: CPU vs GPU vs NPU vs TPU SL

Know the “role sentence” for each, then compare how they’re optimized.

Processor	Role	Typical core design	Best for
CPU	General-purpose processor	Few, powerful cores	Sequential tasks, OS + apps, complex instructions
GPU	Parallel processor (originally graphics)	Many smaller cores (massive parallelism)	Graphics rendering, simulation, AI training
NPU	AI accelerator	Specialized neural-network units	Neural networks efficiently (often inference, low power)
TPU	Google’s type of NPU	Tensor-optimized design	Large-scale deep learning (esp. data centers / cloud)

One-line distinction: CPU = sequential + flexible, GPU = massively parallel, NPU/TPU = neural-network math (very efficient).

4) Dataflow Architecture SL

Definition: Execution is driven by data availability (not mainly by a program counter).

Instructions run when their inputs are ready
Good fit for parallel workloads
Less common as a general-purpose design, but used in specialized processors

SL Exam-Style FAQ (Quick Answers) SL

Why is the Von Neumann bottleneck a problem?

Because the CPU can’t fetch an instruction and access data simultaneously, reducing throughput.

Do all processors use Harvard architecture?

Not purely. Many use modified Harvard: separate instruction/data caches, unified main memory.

Is a TPU the same as an NPU?

A TPU is a specific type of NPU built by Google for large-scale AI workloads.

Which is best for general-purpose computing?

CPU. GPUs/NPUs are specialized accelerators.

HL Extension: What “Modified Harvard” really means HL

HL students should explain this with caches and why it reduces the bottleneck without fully abandoning a unified memory model.

Core idea

Separate instruction cache (I-cache) and data cache (D-cache)
Often separate paths internally (Harvard-like)
But main memory is still unified (Von Neumann-like)

Why it helps

CPU can (often) fetch instruction + data in parallel at cache level
Reduces stalls, increases throughput
Still easier to program than “pure” separate memories

HL diagram (conceptual)

┌───────── I-Cache ─────────┐ CPU front-end ──┤ ├── Unified main memory └───────── D-Cache ─────────┘

HL phrasing: “Modern CPUs are typically modified Harvard: separate I/D caches reduce instruction/data contention, but both ultimately map to a unified address space.”

HL Extension: CPU vs GPU (architectural reasoning) HL

Compare by: core type + control flow + parallelism style.

CPU: fewer cores, high single-thread performance, complex control flow
GPU: many simpler cores, thrives on the same operation across many data items (data-parallel work)
Good HL language: “GPU is throughput-oriented; CPU is latency-oriented.”

Use case argument: if your task is “lots of identical operations” (e.g., pixel shading or matrix ops), GPU tends to dominate. If it’s “branchy logic + mixed tasks”, CPU tends to win.

HL Extension: Dataflow vs Von Neumann control HL

Von Neumann control model

Program counter steps through instruction sequence
Order is explicit in the program
Bottleneck can occur at shared memory/bus

Dataflow control model

No “main” sequential driver in the same sense
Instructions run when inputs are ready
Natural parallelism, good for pipelines / streaming workloads

HL micro-example (conceptual)

Let: A = X + Y B = A * Z Dataflow: (X,Y ready) → compute A (A,Z ready) → compute B No step runs "just because the PC reached it".

HL Exam Prompts (practice) HL

Explain why modified Harvard reduces (but doesn’t remove) the bottleneck.

Separate I-cache and D-cache allow parallel instruction/data access at cache level, reducing contention. However, both still ultimately access unified main memory and shared lower-level resources, so contention can still occur.

Why do TPUs/NPUs often use lower precision arithmetic?

Neural networks can tolerate reduced precision for many operations, so lower precision increases throughput and reduces power/area costs, improving efficiency.

Choose CPU, GPU, or NPU for a workload and justify.

CPU for mixed logic and OS tasks; GPU for highly parallel numeric workloads; NPU/TPU for neural-network inference/training where matrix/tensor operations dominate and efficiency matters.

Mini Quiz (SL + HL) Mixed

Click an answer to get immediate feedback.

Computer Architecture Types IB Computer Science